Redundant Binary Multiplier with Modified Partial Product Generator

TASLEEMA SULTHANA, CH ANIL KUMAR

Abstract


The requirement of the modern computer system is a dedicated and very high speed unique multiplier unit for signed and unsigned numbers. The work mainly deals with in improving multiplication process by using Redundant Binary Technique.The redundant binary in design of high speed digital multiplier is beneficial due to high modularity and carry free addition. Generally,in high radix modified booth encoding algorithm the partial products are reduced in multiplication process. But it yields complexity in producing in generation of hard multiples.Therefore booth encoding scheme along with redundant binary scheme solves this problem by using booth encoding, RB partial product generator,RB partial product accumulator,RB to NB converter stage.In this paper implemented in Verilog HDL


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